An FPGA Implementation of the Digital IF Processor

This document describes the simulation and FPGA implementation of the IIP Radiometer Digital IF Section described in [1]. The digital IF processor presented here is a slightly different to that of [1]. The digital IF processor implemented here is illustrated in Figure 1 where there are four distinct sections; namely demultiplex, FS/4 down conversion, filtering and FS/4 up conversion. The structure differs by keeping the FS/4 down conversion and FIR filter coefficients separate. In the original design the FIR filter coefficients incorporated the ±1 sign changes. Unfortunately the FIR compiler [2] couldn’t synthesize this successfully. The resulting increase in size due to the separation is very small compared to the overall size of the design. This document is broken into four separate sections. The first section illustrates the results of Matlab simulations of the structure shown in Figure 1. Section 2 deals with an implementation of the structure in an Altera APEX FPGA. Section 3 presents simulation results of the FPGA implementation. Finally, Section 4 presents results of a Matlab simulation using recorded data from an AD9054 evaluation board.